Television type display system for displaying information in the form of curves or graphs

ABSTRACT

Television type display system for displaying information in the form of curves or graphs. Code words designating characters are read out of a random access memory and the characters are displayed at fixed normal locations on the display surface of the display device. The normal location of a character on the display surface is determined by the position of the character code word in the memory. Delay code words designating amounts of delay may be associated with characters by being stored in the position in the memory preceding a character code word. The delay code word is employed to hold the character data for each scanline in a buffer for a period of time determined by the delay code word before releasing the data into the video stream. Thus, display of the character is delayed causing it to appear in a location on the display surface shifted from its normal location. A plurality of characters may be displayed in this manner to produce a curve. The system may also be utilized to display data in bargraph format.

United States Gicca et al.

aten' [1 1 TELEVISION TYPE DISPLAY SYSTEM FOR DISPLAYING HNFORMATKON IN THE FORM 01F CURVES OR GRAPHS [75] Inventors: Francis A. Gicca, Bedford; Francis C. Passavant, West Newton; Allen J. Worters, Newton Highlands, all of Mass.

[73] Assignee: GTE Sylvania incorporated,

Stamford, Conn.

[22] Filed: June 21, 1972 21 Appl. No.: 264,970

[52] US. Cl 340/324 AD, 95/45 .1

[51] Int. Cl. G06f 3/14 [58] Field Of Search. 340/324 A, 324 AD; 178/15, 30; 95/45 .1

[56] References Cited I UNITED STATES PATENTS 3,396,377 8/1968 SII'OUI 340/324 AD 3,011,164 11/1961 Gerhardt 340/324 AD Primary Examiner -Donald J. Yusko Assistant Examiner-Marshall M. Curtis Attorney-Norman J. OMalley et al.

CHARACTER COLUMN 0R DELAY ADDRESS CLOCK CODE WORD R (FROM REFRESH MEMORY) GRAPHIC CODE REGISTER DELAY VIDEO BUFFER DELAY DELAY l DELAY I CLOCK GEN,

DELAY 1 BUFFER DELAY 1 vmzo BUFFER DELAYZ BUFFER [57] ABSTRACT Television type display system for displaying information in the form of curves or graphs. Code words designating characters are read out of a random access memory and the characters are displayed at fixed normal locations on the display surface of the display device. The normal location of a character on the display surface is determined bp the position of the character code word in the memory. Delay code words designating amounts of delay may be associated with characters by being stored in the position in the memory preceding a character code word. The delay code word is employed to hold the character data for each scanline in a buffer for a period of time determined by the delay code word before releasing the data into the video stream. Thus, display of the character is delayed causing it to appear in a location on the display surface shifted from its normal location. A plurality of characters may be displayed in this manner to produce a curve. The system may also be utilized to display data in bargraph format.

8 Claims, 14 Drawing Figures Y VIDEO AMPL VIDEO HORlZBiVERT SYNC NO DELAY MUX DELAY l MUX DELAY 2 M UX PATENTEDnsczsmn SHEET 0 BF 7 iv BUN m mom maoo m L m mom mom mom maoo mooo wooo 435 time 51 $.00 mkoo m oo N w w mom mom mom moou M900 M500 .V m N 255 60 PATENTEI] DEC 2 5 I975 SHEET 5 0F 7 ,iilxlix 4 m mom mom wooo mooo Elmo mkoo m m mom mom mom M500 M500 H 500 whoa whoa 4 mon w m mom H 500 mom mom M500 mooo maoo Eo GQ whom I 4 P00 mp mo. mom r mom mooo mooo mom M500 M500 5 3mm time whoa w. .oo mm m? mom mom wooo wooo v m m ZEDJOQ TELEVISION TYPE DISPLAY SYSTEM FOR DISPLAYING INFORMATION IN THE FORM OF CURVES OR GRAPHS BACKGROUND OF THE INVENTION This invention relates to display systems. More particularly it is concerned with apparatus for producing television-like displays of information in graphical form.

Terminal display systems of the type for displaying business data from a computer on television monitors are well knon. These systems are generally similar. A controller is employed to communicate messages to and from a host computer in which data processing tasks are performed. Information to be displayed is transmitted from the controller to refresh memories which store the information being displayed in binary code format. The display stations each employ a standard closed-circuit television monitor and keyboard which permits the operator to communicate with the most computer.

Typically display systems of this general type display information in alphanumeric form. Alphanumeric codes representing the characters to be displayed are loaded from the host computer through the controller and into a refresh memory associated with a display device at the display station. The alphanumeric code words are placed in particular storage positions in the refresh memory. Each storage position designates a specific row and column character location on the face of the display device. Each display station includes a video generator which receives the code words as they are repeatedly read out of the associated refresh memory in timed relationship with the sweeping of the raster scanline pattern. The code words read out for each scanline are converted into a series of data bits. These bits are gated into the video stream to the display device to cause the image of each character to be constructed of several series of dots written during several scanlines. The character represented by a code word is displayed on the face of the display device in the normal location designated by its storage position in the refresh memory.

Although display terminals of this type are satifactory for displaying alphanumeric characters in a regular row and column array of text, they do not permit the display of true curves, histograms, or bargraphs. Since characters may be positioned only in normal locations, graphical displays of information are relatively crude. High quality graphic presentations may be obtained by the use of random access display devices of the type in which deflection amplifiers guide the beam of a cathode ray tube through a pattern of movement permitting characters to be displayed at almost any position on the display surface. However, high-speed, high-quality random access display terminals of this type which permit complete freedom of beam movement and character location are considered inordinately expensive for use in routine business applications.

SUMMARY OF THE INVENTION Improved display systems in accordance with the present invention permit high quality display of graphical information on standard television displays. A system displays characters on a video display means of the type producing images on a display surface be selectively writing on the display surface while repeatedly sweeping a raster scanline pattern over the display surface. The system includes character data memory means for storing character data in a plurality of storage positions, each storage position corresponding to a specific row-column location, or normal" location, on the display surface. The system also includes shift data memory means for storing shifting information in association with character data stored in particular storage positions.

An addressing means causes character data to be read out of the character data memory means. A video signal generating means is coupled to the character data memory means and in response to character data being read out of the character data memory means generates video signals for producing images of characters on the display surface. A control means causes the video signals for producing images of characters not having shifting information associated therewith to be generated in timed relationship with signals for controlling the raster scanline pattern so that images of the characters are produced in the normal locations on the display surface corresponding to the storage position in which the respective character data is stored. The system also includes shifting means which cause the video signals for producing images of particular characters having shifting information associated therewith to be generated in timed relationship with signals for controlling the raster scanline pattern so that images of the particular characters are produced in locations on the display surface shifted from the normal locations as determined by the shifting information associated with the respective characters.

BRIEF DESCRIPTION OF THE DRAWINGS Additional objects, features, and advantages of display systems in accordance with the present invention will be apparent from the following detailed discussion together with the accompanying drawings wherein:

FIG. 1 is a block diagram of a display system employed in the present invention;

FIG. 2 is a block diagram of a video generator in accordance with the present invention for use in the system illustrated in FIG. 1;

FIG. 3A is a representation of a portion of a display surface ofa display device illustrating curves which are produced by limiting characters to their normal locations;

FIG. 3B is a representation of a portion of the display surface of a display device illustrating curves which may be produced by a display system in accordance with the present invention;

FIG. 4A is a chart or map of a portion of a random access digital storage type refresh memory employed in the system of FIG. 1;

FIG. 4B is a representation of a portion of the display surface of a display device illustrating the resulting display produced from the data encoded in the refresh memory of FIG. 4A;

FIG. 5A is also a map of a portion of a refresh memory;

FIG. 5B is a representation of a portion of the display surface illustrating the resulting display produced from the data encoded in the refresh memory of FIG. 5A;

FIG. 6 illustrates several graphic characters which may be employed in the display system of FIG. 1;

FIG. 7A is another map of a portion of a refresh memory;

FIG. 7B is a representation of a portion of the display surface illustrating the resulting display produced from the data encoded in the refresh memory of FIG. 7A;

FIG. 8 is a representation of a portion of the display surface illustrating the display of a plurality of bargraphs;

FIG. 9 is a representation of a portion of the display surface illustrating the display of a different form of bargraphs; and

FIG. 10 is a detailed block diagram of a multiplexer and shift register section of the apparatus.

DETAILED DESCRIPTION OF THE INVENTION General FIG. 1 is a block diagram of an entire display system which at the level of detail shown resembles many known systems as well as systems in accordance with the present invention. FIG. 2 is a detailed block diagramof a video generator in accordance with the present invention which is employed in the system of FIG. 1. The system includes a host computer 10 together with associated peripheral equipment and software and a controller 12 which communicates with the computer through a suitable interface arrangement 11. The system may contain several display stations each including a refresh memory 16, a video generator 17, a video display device 18, and a keyboard 19. Data is transferred to the refresh memories 16 through an input/output buffer 15. The refresh memories 16 and video generators 17 are controlled by a display controller 14 which is also connected to the input/output buffer 15. The keyboards 19 of the individual display stations are connected to the computer 10 through a keyboard interface 13 and the controller 12.

Apparatus ofthe type shown generally-in FIG. 1 typically is employed to display alphanumeric characters in test row-column locations, or normal locations, on the face of the television display device 18 at a display station. More specifically, the refresh memory 16 is divided into an array of storage positions each corresponding to a normal location within a row and column arrangement on the display surface. Each storage position stores a single code word representing an alphanumeric character and each location provides space for displaying a single character. For example, the storage positions in the memory and the character locations on the display surface may be arranged in 100 vertical columns and 40 horizontal rows to provide for displaying up to 4,000 characters of text on the surface of the display device.

Heretofore, when systems of this type have been em played to display graphical information, the limitation of positioning characters only in normal locations severly limited the accuracy and the aesthetics of the resulting display. A set of curves of data displayed in this manner is illustrated in FIG. 3A. Each character of the display is positioned in its appropriate normal location by row and column. In contrast, systems in accordance with the present invention permit shifting of individual characters from their normal locations, thus providing a display of graphical information which more clearly represents a curve as illustrated in FIG. 3B.

As an example of a specific embodiment for purposes of discussion herein, each of the 4,000 normal locations on the surface of the display device occupies a 6 10 dot matrix, 6 dots horizontally and 10 dots vertically. The image of analphanumeric character is constructed by selectively writing dots in the vertical dot columns of 10 dot positions each during tracing of 6 vertical scanlines. In the specific embodiment under discussion the scanlines are traced vertically downward and odd and even scanlines are interlaced during sweeping of alternating fields. Thus, 6 vertical scanlines, 3 in each field, are required to construct the image of a character in a 6 10 dot matrix location. In order to provide separation between characters in adjacent locations, each alphanumeric character is confined to a 5X7 dot configuration. Additional graphic characters may also be displayed which utilize up to the full 6X10 dot matrix as will be explained hereinbelow. As will be made apparent in further discussion of the system in accordance with the present invention, the characters may be shifted vertically from their normal locations and positioned in one of 400 possible locations for each vertical column, or 40,000 possible locations on the face of the display. The characters are shifted in incremental divisions of l dot, or one-tenth of a character location in the vertical dimension.

Codes designating the characters to be displayed are transferred from the computer 10 to appropriate storage positions in the refresh memory 16. If a character is to be positioned on the display in a location shifted from a normal location, a delay code is stored in the storage position designating the previous row of the same column. The delay code designates the amount the associated character is to be delayed or shifted vertically downward from what would be its normal location. The storage positionsin the memory are read out vertically from top to bottom within a single column in timed relationship with the tracing of each scanline by the display controller 14. Thus, during each field, each column of storage positions is addressed in sequence for three successive scanlines. The total number of acriva' esfiiin'esrsr a complete frame of two fields is 6 00.

In the specific embodiment of the present invention as illustrated three different types of code words may be entered in the refresh memory 16 from the computer 10. The code words, which contain eight binary bits, designate either an alphanumeric character, a special graphic character, or an amount of delay. The following table explains the nature of the three types of code words.

BitNo.

0 A x x x x x x Oforeighthbit indicates code for alphanumeric charac- Alphanumeric Character Code Word Graphic Character Code Word yyyyy Delay l-Ozzzzz Code Word 2 z z z z is binary number designating an amount of delay in number of vertical dots.

In the system under discussion the display device 18 5 may include the capability of displaying a character with relatively high or relatively low brightness levels. The seventh bit of the character code words is either a l or a 0 to designate the brightness amplitude.

The various code words are loaded into the storage positions of the refresh memories 16 from the computer through the input/output buffer during appropriate times in the operating cycles of the apparatus under control of the controller 12 and display controller 14. The code words are read out of the refresh memory 16 to the video generator 17 under the control of the display controller 14 in proper timed relationship with the sweeping of the raster scanline pattern of the display device 18. The display controller 14 supplied the timing and control signals to the refresh memory 16 and to the video generator 17. These signals include the horizontal and vertical synchronizing signals for the display device as well as various coordinated clock pulse signals occurring at the scanline rate, the character location rate, and the individual character bit or dot position rate. These signals are repetitive over each op erating cycle of the apparatus during the sweeping of a complete raster scanline frame over the face of the display device 18. The display controller 14 is, therefore, an element of straightforward design for providing a multitude of synchronized pulses at different frequencies which are appropriately gated to the refresh memory l6 and video generator 17 so as to properly coordinateoperations throughout the system.

As a code word is read out of its storage position in the refresh memory 145 by the display controller 14, the code bits designating the character or the amount of delay are loaded into the character or delay code register 27 of the video generator 37 as shown in FIG. 2. At the same time, the portion of the code word designating whether the code is for a delay, an alphanumeric character, or a graphic character, as well as the bit indicating the amplitude is decoded by a decoder 25 and loaded in the delay, alphanumeric or graphic, and amplitude indication register 28. The information on the particular dot column or scanline is received from the display controller 1 and loaded into the dot column address register 26.

The code in the character or delay code register 27 is then applied to the alphanumeric character generator 29, the graphic character generator 30, or the delay register 31 as determined by the appropriate alphanu meric, graphic, or delay signal from the delay, alphanumeric or graphic, and amplitude indication register 28. The character generators 29 and 30 are read-only memories of the wellknown type which are widely employed to convert digital code designations to the appropriate signals for producing the dot images for the particular scanline of the character. The particular scanline is identified by the data from the dot column address register 26. If the code from the character or delay code register 27 is a delay code which is transferred to the delay register 31, the delay arrangement 40 operates to control handling of the associated character code which is read out from the next storage position to be addressed in the refresh memory.

The video buffer control 48 causes the character data from either character generator 29 or 30 to be entered in the no delay video buffer 45 if there was no previous delay code for it to be associated with. If the character data is associated with a delay, it is loaded into the delay 1 video buffer 46 or the delay 2 video buffer 47. The system utilizes the delay I video buffer 46 and the delay 2 video buffer 47 in alternation.

Character data is read out of the video buffers 45, 46, and 47 by the multiplexers 50 and 51 together or by multiplexer 511 alone under control of the respective multiplexer controls 41, 42, and 43. The appropriate multiplexers 5t) and 51 or 51 are selected by the multiplexer controls depending on the amplitude signal. The appropriate multiplexer controls 41, 42, and 43 operate at the proper times with respect to the scanline being traced to cause data to be transferred from the video buffers 45, 46, and 47 to the appropriate shift registers 52 and 53 or 53 and from there to a summing network 5% where it is combined with the synchronizing signals to produce the composite video signali Amplitude information is available by virtue of there being an output either from both of the shift registers 52 and 53 or from only the shift register 53, and this information may be utilized by employing any of various techniques to produce displays of two different intensities.

The no delay multiplexer control 41 enables the proper ones of the multiplexers 50 and 51 or 51 to read out the no delay video buffer 45 at the proper time to cause the resulting image of the data to appear in the normal location on the surface of the display device. The delay arrangement 40 processes the delay information in the delay register 31 so as to cause the delay 1 multiplexer control 42 or the delay 2 multiplexer control 43 to read out the associated character data in the delay ll video buffer 46 or the delay 2 video buffer 417 at the proper time to cause the resulting image of the data to appear in a location on the display surface shifted vertically downward by an amount determined by the delay code.

Detailed Operation No Delay The following is an explanation of the manner of operation of the apparatus of FIGS. l and 2 in producing an image ofa character in its normal location on the display surface of the display device. Alphanumeric text typically would be processed in this manner. An example of this situation is illustrated by processing of the data stored in the storage position for the fourth row of the first column in the portion of the memory map of FIG. 4A for display on the representation of the corresponding portion of the display surface in FIG. 4B.

The storage position for the fourth row of the first column is read out in proper timed relationship with the tracing of an appropriate scanline on the face of the display device by the display controller 14. Information identifying the scanline as to one of six possibilities, thus designating the particular dot column of the character matrix to be produced, is also received from the display controller 14 as explained previously. For the 8-bit code word read out of the memory the eighth bit is a 0, indicating an alphanumeric character, the seventh bit is a l or a 0 indicating the amplitude, and the other 6 bits designate the alphanumeric character F.

The code designating the dot column of the scanline is loaded into the dot column address register 26, and the code bits designating the character F are loaded into the character or delay code register 27. The decoder decodes the information in the 8th and 7th 7 bits and loads information identifying the code as designating an alphanumeric character and also the data on the amplitude in the delay, alphanumeric or graphic, and amplitude indication register 28.

The data in the input registers 26, 27, and 28 is applied to the character generators 29 and 30. Since the delay, alphanumeric or graphic, and amplitude indicaacter in the appropriate dot column of the character location.

The video buffer control 48 receives clock pulses at the character location scanning rate. In response to each clock pulse the video buffer control 48 enables the no delay video buffer unless a delay 1 or delay 2 signal is present, as will be explained hereinbelow. Since there is no delay I or delay 2 signal present in the example under discussion, the no delay video buffer 45 is enabled and the character datafrom the alphanumericcharacter generator 29 together with the amplitude indication from the delay, alphanumeric or graphic, and amplitude indication register 28 are loaded intothe no delay video buffer 45.

The character data stored in the no delay video buffer 45 is read out under control of the no delay multiplexer control 41. The no delay multiplexer control 41 operates on periodic clock pulses which occur at the character location scanning rate. If there is no input signal to the no delay multiplexer control 41 to indicate that the no delay video buffer 45 contains anything except character data which is not to be delayed, the no delay multiplexer control 41 is not inhibited. A clock pulse causes the no delay multiplexer control 41 to 0perate in timed relationship to the tracing of the scanline to enable either both the low amplitude multiplexer and the low and high amplitude multiplexer 51 or only the low and high amplitude multiplexer 51 depending upon the amplitude signal from the no delay video buffer 45. The data bits relating to the character are transferred in parallel from the no delay video buffer 45 to the appropriate parallel-to-serial shift registers 52 and 53 or 53.

Ten bits of character data are entered into the shift registers 52 and 53 or 53 and are clocked out in series at the dot position rate to enter the video stream by way of the summing network 54. Each bit enters the video stream in timed coordination with the tracing of the scanline through the corresponding dot column position at the normal location on the display surface. The series of data bits from the shift registers 52 and 53 or 53 are combined with the horizontal and vertical synchronizing signals from the display controller 14 to produce the composite video signal which is transmitted to the display device 18 to construct the image of the appropriate dot column of the character in its normal location. Upon completion of sweeping through a complete frame of the raster scanline pattern the image of the character is completely constructed in dot matrix form in its normal location as illustrated in the fourth row of the first column in FIG. 4B.

The apparatus operates in a similar manner to construct the image of a graphic character in its normal location on the surface of a display device. The 8-bit graphic character code word includes a l for the eighth bit and a l for the sixth bit. The decoder 25 identifies this information and causes it to be properly loaded in the delay, alphanumeric or graphic, and amplitude indication register 28. Thus, when the data is read out of the input registers 26, 27, and 28, the graphic signal causes the graphic character generator 30 rather than the alphanumeric character generator 29 to be enabled. Processing of the data bits from the graphic character generator 30 then takes place in the same manner as previously described for data bits from the alphanumeric character generator 29.

Detailed Operation One Delay The following is a description of the manner in which the apparatus illustrated in FIGS. 1 and 2 operates to produce an image of a character on the display surface in a location shifted from its normal location. This situation is illustrated, for example, by the code words stored in the second column of the memory map of FIG. 4A and the resulting image shown in FIG. 4B. As shown in FIG. 4A the code word for the character F is stored in the storage position which designates a normal location on the display surface, the third row of the second column. Stored in the storage position for the second row of the second column is an associated delay code word which indicates that the character F is to be displayed in the second column in a location displaced vertically downward from its normal location by eight dot positions.

As the storage positions of the second column are read out in timed relationship with an appropriate scanline, the delay code word is read out first and applied to the video generator 17. The first five bits which designate the amount of delay are loaded in the character or delay code register 27. The decoder 25 decodes the eighth and sixth bits as indicating a delay and enters this information in the delay, alphanumeric or graphic, and amplitude indication register 28.

When the data is read outvof the input registers 26, 27, and 28, the presence of a delay signal from the register 28 activates a delay control 32. The delay control 32 enables the delay register 31 on a subsequent clock pulse so that the delay code from the character or delay code register 27 is placed in the delay register 31. The delay control 32 holds the delay code in the delay register 31 for a period of time equivalent to the tracing of the scanline through ten dots, the vertical dimension of a character location. This period of time is determined by the period of the clock pulses applied to the delay control 32. On the clock pulse upon termination of this period (when the data for the character F is being loaded into the delay 1 video buffer 46 or the delay 2 buffer 47 as will be explained), the delay control 32 produce a delay 1" signal or a delay 2" signal. The delay control 32 includes a flip-flop arrangement which is caused to be triggered by each delay signal and in effect divides by two so that every other delay code is processed as a delay 1 and intervening delay codes are processed as a delay 2. Assuming a delay 1 signal is produced by the delay control 32. the delay 1 signal activates a delay 1 counter 34 causing a count represented by the delay code in the delay register 31 to be loaded into the delay 1 counter 34. At the same time a delay 1 clock generator 33 is also activated. The delay 1 clock generator 33 produces periodic clock pulses at the dot position rate. When the delay 1 clock generator 33 has provided the proper number of clock pulses (eight in this example) to the delay 1 counter 34 causing the delay 1 counter to count down from the count of eight received from the delay register 31 to a count of zero, a delay 1 complete signal is produced by the delay 1 counter. This signal deactivates the delay 1 clock generator 33 and is also applied to the delay 1 multiplexer control 412.

When the delay code from the character or delay code register 27 is applied to the delay register 31, the next storage position in the refresh memory 16 is read out. Thus, the code for the character F is placed in the character or delay code register 27 and the indication that it is an alphanumeric character as determined by the decoder 25 and the amplitude information are stored in the delay, alphanumeric or graphic, and amplitude indication register 28. The alphanumeric signal, character code, and dot column information are applied to the alphanumeric character generator 29 from the input registers 28, 27 and 26, respectively. The alphanumeric chracter generator 29 thus produces the appropriate data bits in the same manner as explained previously.

The data bits pertinent to the character F are applied to the video buffers 45, 46, and 47 by the alphanumeric character generator 29. The video buffer control 48 receives the delay 1 signal from the delay control 32. In response to the delay ll signal the video buffer control 48 inhibits the enabling signal to the :no delay video buffer 45 on the next clock pulse, and instead produces an enabling signal to the delay 1 video buffer 46 on the clock pulse. Thus the data bits pertinent to the character F from the alphanumeric character generator 29 and the amplitude information from the delay, alphanumeric or graphic, and amplitude indication register 28 are loaded into the delay 1 video buffer 46.

Thecharacter data information remains stored in the delay 1 video buffer 46 until the delay 1 counter 34 completes its countdown and the delay 1 complete signal is transmitted to the delay 1 multiplexer control 42. In response to the delay 1 complete signal the delay 1 multiplexer control 42 produces an enabling signal to the appropriate gates of either both the low amplitude multiplexer 50 and the low and high amplitude multiplexer 511 or only to the low and high amplitude multiplexer 51, depending upon the amplitude information from the delay 1 video buffer 46. In the present example, the enabling signal occurs eight dot positions of movement of the scanline later than if there were no delay and the data were being transferred from the no delay video buffer 45. The data bits pertinent to the character are thus transferred through the appropriate multiplexers 50 and 51 or 51 to the associated parallelto-serial shift registers 52 and 53 or 53. The bits are clocked out of the shift registers at the rate of one bit for the tracing of a scanline through one dot position, and pass through the summation network 54 to become part of the composite video signal to the display device.

As illustrated by the character F in the second column of FIG. 4B, by delaying the data bits for each scanline by eight dot positions, the image is constructed in a location which is eight dots lower in the display than its normal location. FIGS. 4A and 4B also indicate the manner in which the information encoded in the third and fourth columns of the refresh memory produce corresponding images on the display surface providing a curve in which each character may be located vertically within a spacing which in the present embodiment is equal to onetenth of a character location.

The video generator operates in a similar manner employing similar corresponding sections and producing similar corresponding signals (indicated as delay 2 in the figures) to process the next delay code word and the character data associated therewith.

Detailed Operation Two Delays The apparatus of FIGS. l and 2 may also be employed to display two curves, which may intersect, as shown in FIG. 3B, in accordance with the memory map of FIG. 5A and the representation of the corresponding display surface of FIG. 58. Such a display requires the processing of two sets of delay information at the same time.

During the processing of the information encoded in the first column of the memory as shown in the memory map of FIG. 5A, the code for one dot delay in the first row and the code for A in the second row results in the character A being produced on the display surface as illustrated in the first column of FIG. SB in accordance with the previous explanation for a single delay. The character F is produced in its normal location in the fourth row of the first column of the display surface in accordance with the previous explanation for no delay.

A more complex situation is illustrated by the second column of the memory illustrated in FIG. 5A. The delay code word for fifteen dots delay which is stored in the zero row of the second column and the code word for the character A which is stored in the first row of the second column are processed during each scanline to produce the appropriate dots for the dot column in the manner explained hereinabove for a single delay.

However, the amount of delay associated with the character A is such that the processing of data pertaining to the character A is not complete before information pertaining to the next character to be displayed in the same column is received from the memory. Assuming the fifteen dot delay data associated with the character A is processed as a delay ll, while the character A data is in the delay 1 video buffer 46 and the delay 1 counter is counting downward from the count of fifteen, the code word for eight dots delay is read out of the memory storage position for the second row of the second column and data is loaded into the input registers 27 and 28 as explained hereinabove. Also as explained previously, when the information is read out of the registers 27 and 28, the delay signal is applied to the delay control 32 and the delay control causes the delay code to be loaded into the delay register 31. At the end of the ten dot holding period, the delay control 32 produces a delay 2 signal causing the count of eight to be transferred from the delay register 31 to the delay 2 counter 36 and activating the delay 2 clock generator 35. The delay 2 clock generator 35 applies clock pulses to the delay 2 counter 36 at the rate of one clock pulse for the tracing of the scanline through one dot position on the display surface.

The code word for the character F is read out of the storage position for the third row of the second column, loaded into the input registers 27 and 28, the information applied to the alphanumeric character generator 29 in. the manner described previously. The video buffer control 48 receives the delay 2 signal from the delay control 32 indicating that the delay associated with the character F is being processed by the delay 2 portion of the delay arrangement and enables the delay 2 video buffer 47 so that the character Fdata from the alphanumeric character generator 29 is loaded into the delay 2 video buffer 47. Thus, the handling of the characters A and F and the processing of their associated delay information proceeds independently of each other without interference.

When the delay 2 counter 36 completes the countdown of eight, it produces a delay 2 complete signal to the delay 2 multiplexer control 43. In response to this signal the delay 2 multiplexer control 43 enables the appropriate gates in either both the low amplitude multiplexer 50 and low and high amplitude multiplexer 51 or only in the low and high amplitude multiplexer 51, depending upon the amplitude information from the delay 2 video buffer 47, transferring the character data bits to the proper parallel-to-serial shift registers 52 and 53 or 53. The data bits are clocked out of the shift registers 52 and 53 or 53 in series and enter the composite video signal through the summation network 54. The eight dots delay during each scanline causes the character F to be constructed in the proper location in the second column of the display surface as shown in FIG. B.

The apparatus operates in the same manner in pro cessing the information for the third column as shown in the memory map of FIG. 5A. In the resulting display as illustrated in FIG. 5B, and also as shown in the curve of FIG. 3B, the two characters are superimposed. The data relating to the two characters is processed independently in the manner explained previously with the character data on the character F in the delay 1 video buffer 46, for example, and its associated delay data processed by the delay 1 counter 34, and with the character data on the character A in the delay 2 video buffer 47 and its associated delay data processed by the delay 2 counter 36. The appropriate gates of the proper multiplexers 50 and 51 or 51 are independently enabled by the proper multiplexer controls 42 and 43 in response to the delay 1 complete and delay 2 complete signals. The data bits become superimposed in one or both of the shift registers 52 and 53 or 53 and enter the video stream combined to produce the images of the two characters as illustrated in the third column of FIG. 5B.

Bargraph Type Displays The system in accordance with the invention may be employed to display graphical data in formats other than the curves shown in FIGS. 38 and FIGS. 4B and 5B. Specifically, data may be displayed in vertical bargraph format. FIG. 6 illustrates examples of graphic characters which may be displayed to construct bargraphs on the surface of a display device. The specific char ste s r d si na e i he 8-bit e for p i characters as explained hereinabove. Each graphic character as shown irr FIG. 6 occupies the 6x10 dot matrix of a character location. Graphic characters (a), (b), (c), and (j), are solid characters (every dot). Graphic characters (d), (e), and (f) are half-tone characters (every other dot), and characters (g), (h). and (i) are quarter-tone characters (every fourth dot).

These characters may be employed to produce bargraph displays of various types such as those illustrated in FIGS. 8 and 9. By employing the apparatus in the manner described hereinabove, the height of each bar can be positioned within an accuracy of one dot, onetenth of the vertical height of a character location. Operation of the apparatus of FIGS. I and 2 to produce such a display may be understood by reference to the map of the portion of the memory shown in FIG. 7A and the resulting portion of the display as illustrated in FIG. 78. For purposes of illustration the narrow bar character (j) of FIG. 6 is shown in this example.

As the storage positions in the memory for the column are addressed, the code word for six dots delay is read out of the second row. The delay code is processed in the manner explained hereinabove as a delay 1, for example. The code word for the bar is read out of the storage position for the third row, processed in the manner explained previously and the data bits from the graphic character generator 30 are placed in the delay I video buffer 46. After the six dot countdown by the delay 1 counter 34, the delay 1 complete signal to the delay 1 multiplexer control 42 causes the data bits from the delay 1 video buffer 46 to enter the video stream by way of the appropriate multiplexers 50 and 51 or 51 and shift registers 52 and 53 or 53. The resulting image of the bar is displaced six dots vertically downward as shown in FIG. 7B and labeled first character.

When the code word for the bar from the fourth row is received, the absence of a delay signal being associated therewith causes the video buffer control 48 to load the character data bits in the no delay video buffer 45. The no delay multiplexer control 41 causes these bits to enter the video stream at the appropriate time so that the resulting image is produced in its normal location, labeled second character in FIG. 7B. As shown in FIG. 7B portions of the two characters overlap, but the manner in which the images are constructed is such that the entire bar is uniform in appearance.

The code words for the bar characters for the third and fourth rows are read out and processed with no delay as explained previously to produce a continuous bar extending to the desired baseline of the graph. FIG. 8 illustrates a display of a set of bars constructed in the foregoing manner. The upper level of each bar can be positioned within a degree of accuracy of one dot, onetenth of a character location.

Similarly, code words for the graphic characters (a) through (i) of FIG. 6 may be utilized to produce graphical displays such as shown in FIG. 9. Each bar may be several character columns wide. For the graphic characters (a), (b), and (c) the upper levels may be positioned to within one dot. In order for the bars produced with the characters (d) through (i) to appear uniform, the delay must be in even numbers of dots. As illustrated by the graphs shown in FIG. 9, by using various solid, half-tone, and quarter-tone characters, bars having different appearances may be constructed. Multiplexer and Shift Register A more detailed block diagram of a multiplexer 51 and shift register 53 is illustrated in FIG. 10. The other multiplexer 50 and shift register 52 are similar. The shift register 53 includes ten flip-flop stages FFl-FF 10, one for each data bit in a character dot column. The occurrence of a cl'ock pulse at the C input sets each flip-flop to produce an output signal at its output if there is a signal present at its D input. If no signal is I present at the D input, a clock pulse resets the flip-flop and no output signal is produced.

The multiplexer 51 includes ten groups of three AND gates 61-70 a group associated with each flip-flop. Each 'AND gate has two inputs. A first input of one AND gate of one group 61 is connected to the no delay video buffer to receive the first character data bit therefrom and the second input is connected to the no delay multiplexer control 41 to receive a no delay readout pulse therefrom. A second AND gate of the group 61 is connected to the delay 11 video buffer 46 to receive the first character data bit therefrom, and to the delay 1 multiplexer control 42 to receive a delay 1 readout pulse therefrom. The third gate of the group 61 is connected in similar fashion to receive the first character data bit from the delay 2 video buffer 17 and the delay 2 readout pulse from the delay 2 multiplexer control 43. A second group of AND gates 62 are appropriately connected to receive the second character data bits from the video buffers 45, an, and 47 and the read out pulses from the multiplexer controls 41, 42, and 43. The other groups of AND gates are also appropriately connected in similar fashion.

The outputs of each group of AND gates 61-70 are connected to an associated OR gate 71-80. The outputs of each OR gate except for the first OR gate 80 in sequence are connected to an associated second OR gate 81-89. A second input of each second OR gate 81-89 is connected to the output of the previous flipflop in sequence, and its output is connected to the D input of its associated flip-flop. The output of the first OR gate 80 is connected directly to the D input of its associated flip-flop F1 10.

The multiplexer 51 operates in response to a readout pulse from a multiplexer control 41, A2, or 43 to apply the ten data bits from the respective video buffer 45, 46, or 47 to the D input of the corresponding 10 flipflops FFl-FFIO. The data bits are loaded into. the flipflops on the next clock pulse and on subsequent clock pulses are moved along the sequence of flip-flops to be transferred out serially from the output of the last flipflop in the sequence FFll to the summing network 54 to become part of the video stream. The clock pulse rate is equal to the dot position scanning rate.

It can be seen that the reading out of the video buffers 45, 46, and 417 is independently controlled by the respective multiplexer controls 41, 42, and 43. Thus, the data bits from one of the buffers can be read out while those from another are in the shift register, causing the two characters to be superimposed-on the display surface. This situation is illustrated by processing the information in the third column of FIGS. 5A and 58.

Data bits for a scanline of the character F are in the delay 1 video buffer do and data bits for the scanline of the character A are in the delay 2 video buffer 47. During the scanline, a delay 1 readout pulse is produced by the delay 1 multiplexer control 42 applying the data bits for the character F from the delay 1 video buffer 46 to the appropriate flip-flops FF1-FF10 of the shift register. The next clock pulse loads the data bits into the flip-flops thereby clocking the first data bit into the video stream. On the next clock pulse the data bits each shift one flop-flop to the right, and the second data bit for the character F enters the video stream.

A delay 2 readout pulse is then produced by the delay 2 multiplexer control 43 applying the data bits for the character A from the delay 2 video buffer 47 to the appropriate flip-flops FF 1-F F10 of the shift register. The next clock pulse shifts the data bits for the character F one stage to the right placing the third bit in the video stream. At the same time the data bits for the character A are loaded into the flip-flops FFl-FF10 and the first data bit for the character A enters the video stream.

That is, if either the data bit for the character F applied to a particular flop-flop from a previous flip-flop in the se-quence or the data bit for the character A applied to the particular flip-flop from the delay 2 video buffer 47 is a 1, then the flip-flop will be set to produce an output signal. In this manner, data bits from one video buffer are combined with or caused to overlap those from another video buffer, and the resulting image displayed is two characters superimposed as illustrated in the third column of FIG. 5B.

Thus, as shown herein systems in accordance with the invention may be employed to display information in the form of bargraphs and curves which are esthetically pleasing and exhibit a high degree of accuracy. Characters are not limited to display in only the 4000 normal locations, but may b'ified iri anyone of 40,000 possible locations without the necessity of employing a memory of correspondingly increased size. The capability of the system to superimpose displayed characters permits the construction of sets of curves which maintain their continuity and smoothness at crossover points as shown in FIGS. 3B and 5B. In addition, this capability makes possible the accurate positioning of the upper level of bargraphs of uniform appearance as illustrated in FIG. 7B and also in FIGS. 8 and 9.

While there has been shown and described what is considered a preferred embodiment of the present invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention as defined by the appended claims.

What is claimed is:

1. A system for displaying characters on a video display means of the type producing images on a display surface by selectively writing on the display surface while repeatedly sweeping a raster scanline pattern over the display surface, said system including in combination memory means for storing coded data in a plurality of storage positions, each storage position corresponding to a normal location on the display surface, said coded data being a digital character code word representing a character to be displayed or being a digital delay code word representing an amount of delay associated with the digital character code word stored in a particular storage position;

memory addressing means for reading out digital code words from said memory means;

video signal generating means coupled to said memory means and operable in response to a digital character code word being read out of a storage position in the memory means to generate video signals for producing an image of the character on the display surface;

control means operable in response to a digital character code word being read out of a storage position in the memory means and in the absence of a digital delay code word associated therewith to cause the video signal generating means to generate video signals for producing an image of the character on the display surface in timed relationship with signals for controlling the raster scanline pattern so that the image of the character is produced on the display surface in its normal location corresponding to the storage position in which the respective digital character code word is stored; and

delay means including first means operable to store data representing the amount of delay of a digital delay code word and to store data related to the associated digital character code word in response to a digital character code word and an associated digital delay code word being read out of said memory means, second means operable in response to data representing an amount of delay being stored in said first means to measure the amount of delay, and third means operable in response to completion of the amount of delay measured by the second means to read out the data re-' lated to the associated digital character code word from the first means to the video signal generating means whereby the video signal generating means generates video signals for producing the image of the character on the display surface in a location displaced from. its normal location in the direction of tracing of-the individual scanlines by an amount determined by the amount of delay represented by the digital delay code word.

2. A system for displaying characters in accordance with claim 1 wherein the storage positions of said memory means are arranged in an array designating rows and columns of corresponding normal locations on the display surface;

said memory addressing means reads out digital code words from the storage positions designating a column in sequence for each tracing ofa scanline; and

a digital delay code word stored in a storage position is associated with the digital character code word stored in the adjacent storage position next in the sequence.

3. A system for displaying characters in accordance with claim 2 wherein said delay means includes delay data storage means for storing data representing an amount of delay read out of said memory means; first character data storage means for storing data relating to the associated character read out of said memory means subsequent to reading out data on an amount of delay; and

delay readout control means coupled to said delay data storage means and to said first character data storage means and operable to read out the data relating to the character stored in the first character data storage means upon completion of the amount of delay represented by the data stored in the delay data storage means and cause the video signal generating means to generate video signals for producing an image as determined by the data relating to the character.

4. A system for displaying characters in accordance with claim 3 including input decoding means coupled to said memory means and operable to produce a delay signal in response to a digital delay code word being read out of said memory means;

and wherein said delay means includes delay input control means coupled to said input decoding. means and operable in response to said delay signal to cause data representing the amount of delay to be stored in said delay data storage means and also operable in response to said delay signal to cause subsequent data relating to the associated character to be stored in said first character data storage means.

5. A system for displaying characters in accordance with claim 4 wherein said delay readout control means includes counting means coupled to said delay data storate means for receiving a count representative of the amount of delay stored in the delay data storage means,' the count representing a numer of incremental divisions of the dimension of a location on the display surface along the direction in which the scanlines are traced;

said counting means being operable to receive periodic clock pulses and to produce. an indication when the number of clock pulses received equals the count received from said delay data storage means;

clock pulse generating means for applying periodic clock pulses to said counting means when activated, the clock pulses occurring at the rate of one clock pulse for the tracing of a scanline through one incremental division;

counting control means for applying the count representative of the amount of delay stored in the delay data storage means to the counting means and for activating said clock pulse generating means when data relating to the associated character is loaded into said first character data storage means; and delay readout means operable in response to said indication to cause the data relating to the character stored in the first character data storage means to be read out of the first character data storage means and the video signal generating means to generate video signals for producing an imgae as determined by the data relating to the character.

6. A system for displaying characters in accordance with claim 5 including r a second character data storage means for storing data relating to character data not associated with an amount of delay;

and wherein said video signal generating means includes video output means coupled to said first character data storage means and to said second character data storage means and operable to convert character data applied thereto to a stream of video signals in timed relationship with the tracing of a scanline; and

said control means includes input control means coupled to said second character data storage means for causing data relating to a character to be stored therein in the absence of an associated amount of delay, and

output control means coupled to said video output means and operable to apply the data stored in the second character data storage means thereto in timed relationship with the tracing of a scanline to cause the image to be produced in its nor-' mal location on the display surface; and

the delay readout means of the delay readout control means is coupled to said video output means and is operable to apply the data stored in the first character data storage means thereto in response to said indication from said counting means;

whereby upon time coincidence of data being applied to the video output means from the second character data storage means and from the first character data storage means, the stream of video signals generated by the video output means consists of signals for causing images related to the two characters to be superimposed.

7. A system for displaying characters in accordance with claim 6 wherein said video output means includes a shift register having a plurality of stages arranged in succession, the number of stages being equal to the number of incremental divisions of the dimension of a location on the display surface along the direction in which the scanlines are traced, each stage of said shift register having .an output terminal, a signal input terminal and a clock input terminal; a like plurality of pairs of AND gates, each pair being associated with a different stage of said shift register, a first input connection of the first AND gate of each pair being connected together and coupled to said output control means of said control means, a second input connection of the first AND gate of each pair being coupled to the second character data storage means, a first input connection of the second AND gate of each pair being connected together and coupled to said delay readout means of the delay readout control means, and a second input connection of the second AND gate of each pair being coupled to the first character data storage means; like plurality of first OR arrangements each associated with a different pair of AND gates, each first OR arrangement having a first input connection connected to the output connection of the first AND gate of its associated pair and a second input connection connected to the output connection of the second AND gate of its associated pair; and a like plurality minus one of second OR arrangements each associated with a different stage of the shift register except for the first stage in the succession, each second OR arrangement having a first input connection connected to the output connection of the associated first OR arrangement, a second input connection connected to the output connection of the previous stage in the succession, and an output connection connected to the signal input terminal of its associated stage, the output connection of the first OR arrangement associated with the first stage in the succession being connected to the signal input terminal of its associated stage;

means connected to the clock input terminals for applying clock pulses thereto, the clock pulses occurring at the rate of one clock pulse for the tracing ofa scanline through one incremental division; and a video signal output terminal connected to the output terminal of the final stage of the succession. 8. A system for displaying characters in accordance with claim 6 further including third character data storage means for storing data relating to the associated character read out of said memory means subsequent to reading out data on an amount of delay;

and wherein said delay input control means includes means operable, in response to a delay signal occurring subsequent to a previous delay signal causing character data to be stored in the first character data storage means, to cause subsequent data relating to a character to be stored in said third character data storage means;

and wherein said delay readout control means also includes second counting means coupled to said delay data storage means for receiving a count representative of the amount of delay stored in the delay data storage means, the count representing a number of incremental divisions of the 'dimension ofa location on the display surface along the direction in which the scanlines are traced; said second counting means being operable to receive periodic clock pulses and to produce an indication when the number of clock pulses received equals the count received from said delay data storage means; second clock pulse generating means for applying periodic clock pulses to said second counting means when activated, the clock pulses occurring at the rate of one clock pulse for the tracing of a scanline through one incremental division; second counting control means for applying the count representative of the amount of delay stored in the delay data storage means to the second counting means and for activating said second clock pulse generating means when data relating to the associated character is loaded into said third character data storage means; and second delay readout means coupled to said video output means and operable in response to said indication to cause the data relating to the character stored in the third character data storage means to be read out of the third character data storage means and the video signal generating means to generate video signals for producing an image as determined by the data relating to the character. 

1. A system for displaying characters on a video display means of the type producing images on a display surface by selectively writing on the display surface while repeatedly sweeping a raster scanline pattern over the display surface, said system including in combination memory means for storing coded data in a plurality of storage positions, each storage position corresponding to a normal location on the display surface, said coded data being a digital character code word representing a character to be displayed or being a digital delay code word representing an amount of delay associated with the digital character code word stored in a particular storage position; memory addressing means for reading out digital code words from said memory means; video signal generating means coupled to said memory means and operable in response to a digital character code word being read out of a storage position in the memory means to generate video signals for producing an image of the character on the display surface; control means operable in response to a digital character code word being read out of a storage position in the memory means and in the absence of a digital delay code word associated therewith to cause the video signal generating means to generate video signals for producing an image of the character on the display surface in timed relationship with signals for controlling the raster scanline pattern so that the image of the character is produced on the display surface in its normal location corresponding to the storage position in which the respective digital character code word is stored; and delay means including first means operable to store data representing the amount of delay of a digital delay code word and to store data related to the associated digital character code word in response to a digital character code word and an associated digital delay code word being read out of said memory means, second means operable in response to data representing an amount of delay being stored in said first means to measure the amount of delay, and third means operable in response to completion of the amount of delay measured by the second means to read out the data related to the associated digital character code word from the first means to the video signal generating means whereby the video signal generating means generates video signals for producing the image of the character on the display surface in a location displaced from its normal location in the direction of tracing of the individual scanlines by an amount determined by the amount of delay represented by the digital delay code word.
 2. A system for displaying characters in accordance with claim 1 wherein the storage positions of said memory means are arranged in an array designating rows and columns of corresponding normal locations on the display surface; said memory addressing means reads out digital code words from the storage positions designating a column in sequence for each tracing of a scanline; and a digital delay code word stored in a storage position is associated with the digital character code word stored in the adjacent storage position next in the sequence.
 3. A system for displaying characters in accordance with claim 2 wherein said delay means includes delay data storage means for storing data representing an amount of delay read out of said memory means; first character data storage means for storing data relating to the associated character read out of said memory means subsequent to reading out data on an amount of delay; and delay readout control means coupled to said delay data storage means and to said first character data storage means and operable to read out the data relating to the character stored in the first character data storage means upon completion of the amount of delay represented by the data stored in the delay data storage means and cause the video signal generating means to generate video signals for producing an image as determined by the data relating to the character.
 4. A system for displaying characters in accordance with claim 3 including input decoding means coupled to said memory means and operable to produce a delay signal in response to a digital delay code word being read out of said memory means; and wherein said delay means includes delay input control means coupled to said input decoding means and operable in response to said delay signal to cause data representing the amount of delay to be stored in said delay data storage means and also operable in response to said delay signal to cause subsequent data relating to the associated character to be stored in said first character data storage means.
 5. A system for displaying characters in accordance with claim 4 wherein said delay readout control means includes counting means coupled to said delay data storate means for receiving a count representative of the amount of delay stored in the delay data storage means, the count representing a numer of incremental divisions of the dimension of a location on the display surface along the direction in which the scanlines are traced; said counting means being operable to receive periodic clock pulses and to produce an indication when the number of clock pulses received equals the count received from said delay data storage means; clock pulse generating means for applying periodic clock pulses to said counting means when activated, the clock pulses occurring at the rate of one clock pulse for the tracing of a scanline through one incremental division; counting control means for applying the count representative of the amount of delay stored in the delay data storage means to the counting means and for activating said clock pulse generating means when data relating to the associated character is loaded into said first character data storage means; and delay readout means operable in response to said indication to cause the data relating to the character stored in the first character data storage means to be read out of the first character data storage means and the video signal generating means to generate video signals for producing an imgae as determined by the data relating to the character.
 6. A system for displaying characters in accordance with claim 5 including a second character data storage means for storing data relating to character data not associated with an amount of delay; and wherein said video signal generating means includes video output means coupled to said first character data storage means and to said second character data storage means and operable to convert character data applied thereto to a stream of video signals in timed relationship with the tracing of a scanline; and said control means includes input control means coupled to said second character data storage means for causing data relating to a character to be stored therein in the absence of an associated amount of delay, and output control means coupled to said video output means and operable to apply the data stored in the second character data storage means thereto in timed relationship with the tracing of a scanline to cause the image to be produced in its normal location on the display surface; and the delay readout means of the delay readout control means is coupled to said video output means and is operable to apply the data stored in the first character data storage means thereto in response to said indication from said counting means; whereby upon time coincidence of data being applied to the video output means from the second character data storage means and from the first character data storage means, the stream of video signals generated by the video output means consists of signals for causing images related to the two characters to be superimposed.
 7. A system for displaying characters in accordance with claim 6 wherein said video output means includes a shift register having a plurality of stages arranged in succession, the number of stages being equal to the number of incremental divisions of the dimension of a location on the display surface along the direction in which the scanlines are traced, each stage of said shift register having an output terminal, a signal input terminal and a clock input terminal; a like plurality of pairs of AND gates, each pair being associated with a different stage of said shift register, a first input connection of the first AND gate of each pair being connected together and coupled to said output control means of said control means, a second input connection of the first AND gate of each pair being coupled to the second character data storage means, a first input connection of the second AND gate of each pair being connected together and coupled to said delay readout means of the delay readout control means, and a second input connection of the second AND gate of each pair being coupled to the first character data storage means; a like plurality of first OR arrangements each associated with a different pair of AND gates, each first OR arrangement having a first input connection connected to the output connection of the first AND gate of its associated pair and a second input connection connected to the output connection of the second AND gate of its associated pair; and a like plurality minus one of second OR arrangements each associated with a different stage of the shift register except for the first stage in the succession, each second OR arrangement having a first input connection connected to the output connection of the associated first OR arrangement, a second input connection connected to the output connection of the previous stage in the succession, and an output connection connected to the signal input terminal of its associated stage, the output connection of the first OR arrangement associated with the first stage in the succession being connected to the signal input terminal of its associated stage; means connected to the clock input terminals for applying clock pulses thereto, the clock pulses occurring at the rate of one clock pulse for the tracing of a scanline through one incremental division; and a video signal output terminal connected to the output terminal of the final stage of the succession.
 8. A system for displaying characters in accordance with claim 6 further including third character data storage means for storing data relating to the associated character read out of said memory means subsequent to reading out data on an amount of delay; and wherein said delay input control means includes means operable, in response to a delay signal occurring subsequent to a previous delay signal causing character data to be stored in the first character data storage means, to cause subsequent data relating to a character to be stored in said third character data storage means; and wherein said delay readout control means also includes second counting means coupled to said delay data storage means for receiving a count representative of the amount of delay stored in the delay data storage means, the count representing a number of incremental divisions of the dimension of a location on the display surface along the direction in which the scanlines are traced; said second counting means being operable to receive periodic clock pulses and to produce an indication when the number of clock pulses received equals the count received from said delay data storage means; second clock pulse generating means for applying periodic clock pulses to said second counting means when activated, the clock pulses occurring at the rate of one clock pulse for the tracing of a scanline through one incremental division; second counting control means for applying the count representative of the amount of delay stored in the delay data storage means to the second counting means and for activating said second clock pulse generating means when data relating to the associated character is loaded into said third character data storage means; and second delay readout means coupled to said video output means and operable in response to said indication to cause the data relating to the character stored in the third character data storage means to be read out of the third character data storage means and the video signal generating means to generate video signals for producing an image as determined by the data relating to the character. 